1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device having two-transistor, one-capacitor type dual-port memory cells.
2. Description of the Background Art
While a conventional DRAM (Dynamic Random Access Memory) generally consists of 1-transistor, one-capacitor type memory cells, various types of memory configurations have been developed to meet demand for mass storage and speed up.
In a case of the memory cells of a DRAM, for example, two-transistor, one-capacitor type memory cells are proposed so as to enable high-rate data access in the same manner as the memory cells of an SRAM (Static Random Access Memory).
Since the present invention is intended at a two-transistor, one-capacitor type memory cell, the two-transistor, one-capacitor type memory cell will be also simply referred to as “memory cell” in the following description.
FIGS. 16A and 16B are block diagrams of a conventional two-transistor, one-capacitor type memory cell.
Referring to FIG. 16A, two transistors NTr and RTr and one capacitor CC are provided per memory cell. Word lines NWL and RWL arranged in parallel are connected to the gates of transistors NTr and RTr, respectively. In addition, bit lines RBL and NBL arranged in parallel cross two word lines NWL and RWL. Transistors RTr and NTr are connected in series between bit lines RBL and NBL through a node NC. Further, node NC is connected to capacitor CC which holds a charge as data.
In this two-transistor, one-capacitor type memory cell, if word line NWL is set at, for example, “H” level, data can be written or read from bit line NBL side to capacitor CC. If word line RWL is set at “H” level, data can be written or read from bit line RBL side to capacitor CC. It is, therefore, possible for two systems to simultaneously access one memory cell and to thereby perform high-rate data access in an entire chip.
Here, the cell layout of the conventional two-transistor, one-capacitor type memory cell will be considered.
FIG. 16B is a layout view of the memory cell described in FIG. 16A.
Referring to FIG. 16B, the pattern of an active region ENB which forms two transistors RTr and NTr arranged in series between two bit lines RBL and NBL will be considered.
Here, in order to connect word lines NWL and RWL to the gates of transistors NTr and RTr, respectively, and to arrange word lines NWL and RWL orthogonal to the bit lines, it is necessary to form active region ENB which forms the transistors into an S-shaped pattern.
If this pattern is formed, it is necessary to secure an active region having a minimum predetermined distance between bit lines RBL and NBL so as to provide two bit lines RBL and NBL in parallel without causing a short-circuit therebetween.
According to such a configuration, since the area of a junction section, which corresponds to node NC, between the active region and a substrate is large, the charge held by capacitor CC are leaked to the substrate from this junction section. That is, junction leak current is excessively generated, with the result that so-called memory cell refresh time is disadvantageously shortened.